Dynamic random access memories (DRAMs) are available in many different configurations. DRAMs may be configured to have different memory densities, different numbers of memory banks, different input/output (I/O) widths, different numbers of prefetch bits, different functions, and so on. Designing a DRAM having a particular configuration takes a substantial amount of time. Each time a particular function of a DRAM is changed, the semiconductor chip providing the DRAM is redesigned through a partial or full layer change. In some DRAM chips, the top interconnects may be modified to alter the configuration of the DRAM to shorten the design cycle time. In some cases, for DRAM chips having I/O widths of ×4, ×8, and ×16, bonding, fusing, or metal options may be used to alter portions of the configuration of the DRAM chip. Changing the top interconnects, however, still requires considerable design and fabrication time.
Typical DRAM chips with ×32 I/O widths, however, require a chip redesign for each change of the configuration. For example, if the number of prefetch bits is modified or the number of memory banks is modified a full layer change is required. Memory density may be increased in some cases by stacking dies to form multi-chip packages (MCPs). While multi-chip packages can be used to obtain a desired memory density, multi-chip packages cannot be used to configure other functions such as the number of prefetch bits, I/O width, number of memory banks, and so on. These other functions still require a partial or full layer change, which requires considerable design and process time to implement.
For these and other reasons, there is a need for the present invention.